The present invention is related to testing of logic circuit designs and, in particular, to compaction of test response data.
Testing of complicated digital logic circuits requires the analysis of a large amount of test response data. A variety of output compaction techniques have been devised for reducing the size of test response data stored in test memory. Techniques to reduce output responses can be classified into two basic categories: “spatial compaction” and “temporal compaction.” Temporal compaction compresses output responses over a period of time into a signature, the signature being significantly smaller than the size of even a single uncompressed output response. Spatial compaction, on the other hand reduces response data volume by reducing the number of outputs that are observed by the automatic test equipment (ATE).
A key barrier to effective output response compaction is the presence of what are referred to as “unknown” values when computing the good-circuit responses. Unknown values can occur for many reasons: the presence of non-scan flip-flops, embedded memories, tristate buffers, the limitation in accuracy of simulation, etc. For a simple spatial compactor built with XOR trees, an output that has a fault effect can appear along with an unknown value at a given scan shift cycle, resulting in the masking of the fault effect. The fault effect cannot be observed at the output of the compactor during that cycle. It is difficult and costly to eliminate all unknown sources from the design, and, thus, it is preferable that the output response compaction technique take into account the presence of unknown values. FIG. 1A depicts one such prior art spatial compaction scheme referred to in the art as an “X-compactor.” See S. Mitra and K. S. Kim, “X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction,” IEEE International Test Conference, pp. 311-20 (2002). The outputs of every scan-chain depicted in FIG. 1B are connected to three outputs, and the outputs of no two scan chains are connected to the same three outputs, thereby ensuring that an error can be observed without being masked even if the error is scanned out along with an unknown value at a clock cycle. FIG. 1B depicts an example of another prior art spatial compaction scheme referred to as a “block compactor.” See C. Wang et al., “On Compacting Test Response Data Containing Unknown Values,” ACM/IEEE International Conference on Computer Aided Design, pp. 855-62 (November 2003). The block compactor uses flip-flops arranged as depicted in FIG. 1B as well as XOR gates to increase the possible combinations of scan chains that can be connected to the XOR array.
Although all of these spatial compaction schemes guarantee that no single error value is masked by a single unknown value, they unfortunately provide varying probabilities of unknown masking when multiple unknown values are present among responses. It would be advantageous to have a more analytical approach to spatial compaction which allowed for the systematic derivation of masking probability in designing an optimal compactor configuration.